force_type confusion

1. This is just the way Verilog works, and the synthesis tool assumes each always is a separate peice of circuitry. VHDL on the other hand mandates that multiple processes driving the same signal cause multiple drivers, so similar code in VHDL will produce X:

signal r : std_logic;
process(clk)
begin
  if rising_edge(clk) then
    r <= '1';
  end if;
end process;
process(clk)
  if rising_edge(clk) then
    r <= '0';
  end if;
process;

This will give you an X value on r.

2. Not quite sure what exactly you're trying to do. In An FPGA, you cannot connect multiple signals together - the hardware doesnt allow it. The only place it is possible is the IO tristates, and it is only possible to drive an internal signal against an external one. You'll need to do multiple assigns to get the tri states working:

assign io = (enable) ? a : 1'bz;

assign a = (~enable) ? io : 1'bz;

Of course, you would only use one of the above in the chip. The other would be in a testbench.