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Always blocks all run in parrellel. This is not a programming language, but a hardware description language. Think of always blocks as infinite loops that get called whenever the condition after the @ is triggered. All always block run and function in parrallel. Think of them as two parrallel circuits.
1. Both always blocks are diving r1_reg. Imagine 2 circuits each connected to the same wire. One drives 0, the other drives 1. Which one wins? you dont know, so the result is X, because reg is a 4 state type, and allows multiple drivers. If you had used blocking assignments, then a race condition will occur. The result WILL depend on compile order, and it likely will fail in synthesis. Moral of the story - dont use blocking assignments in always blocks.
2. these are not gates, they are variable types. If you use system verilog, there are many more types. Stick to reg and wire, and you'll be less confused (or if it's SystemVerilog, just make everything the logic type, or integer).
3. You have multiple drivers on a2. Its pretty clear as you're assigning a2 to two different things.
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@1:
"Always blocks all run in parrellel. Think of always blocks as infinite loops ..."
Say an infinite loop is running, and upon posedge@clk, the programming language's event is generated, and the two always which were registered to the callback table would both get called. However, since we must assume there is a single thread running (almost 100% since modelsim runs on 1-core machine), there is always an order, or always an BL or JMP x86 jumping instruction executed first for one of the "always" before then for the other, so "clk" always get assigned twice at different host machine CPU cycle, it is not strict to say they run in "parallel". If the internal type definition for "clk" were to support contention and in this case were designed to produce "X", it requires such design which records each exact assignment time, and for each group of equivalent assignment instant time, do a value resolution. But just as in our example, we never got "X" but instead only the "later" assigned value. Sad!
@2:
I know they are not gates. I just cannot find way to connect multiple wires to them, for example effectively shorting two (or more) IO output together while making one of them std1 and another std0. I didn't find grammar to do that.
For @1 and @2, could you show runnable verilog example which could produce "X" result in modelsim wave viewer?
greg
Honored Contributor
