force_type confusion

I did ponder on your answer carefully, but still have questions.

Failure 1:

In real circuits, different module/block execute in parallel. But in modelsim, as all were compiled and executes linearly according to a state machine, I doubt if “ambiguity/contention” can be simulated.

For example in a contrived example:

reg r1_reg;

output r1;

always @ (posedge clk)

begin

r1_reg<=1;

end

always @ (posedge clk)

begin

r1_reg<=0;

end

assign r1=r1_reg;

as we run it, we always hit the first "always" before the second, so r1_reg forever is 0. Since HDL compiler always need to sort/give order to blocks before they can be arranged to execute, perhaps it is unavoidable and we could never easily simulate such racing/contention?

Failure 2:

wire, tri, wand,wor,buf,not: grammars of all these gates in Verilog are limited to strict logical expressions (+, &&, ^ operators, etc. Could you give counterexample?), and we failed to construct ambiguous drivers with this.

Failure 3:

input a0,a1;

output a2;

assign a2=a0;

assign a2=a1;

Quartus compiler fail and gives “a2 already assigned to a0” remark.

Could you give nontrivial example to contrive multiple driver ambiguity in Verilog, and give remarks to the 3 failure above?

greg