Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Force synthesis to fail if RAM cannot be inferred?

Hi, we have a design where there are a few large memories, declared as verilog reg[][]'s, which must be implemented as M9Ks. The design can't possibly fit the device or meet timing if they are imple...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

If you're going to do that, you might as well just instantiate the ALTSYNCRAM directly.

The only time I see using a parameterised module like this being useful, that simply infers a ram internally, is when you need cross vendor compatibility.

Because using the megawizard doesnt let you paramterise your block, or use your design in another vendor's tools.

--- Quote End ---

I'm glad at least one person here understood my question.