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Altera_Forum's avatar
Altera_Forum
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12 years ago

Fitter pin locations

I've run through Fitter without location constraints. I want to list all the pin locations including I/O banks that the tool assigned. In Pin Planner, I see the list of pins and Fitter Location but the I/O Bank column is empty. In Chip Planner, I haven't figured out how to display the I/O list of signals with all the I/O properties. Is there a way to list them?

I've gone through some of the pdfs but I find alot of details on pin planning and not post-fit analysis. I would like to see where in the device these pins are located. Any help is much appreciated.

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Assignments -> Back-Annotate -> Pins & Device. They'll all now be hard assignments, but you'll get all the info you want and can work from there. It's also easy to delete in the Assignment Editor, as you can use the top-right filter of Locations, select them all and delete them.

    I believe the Fitter Report's Input/Output and Bidir Pin reports will say what I/O bank they were in too, if you don't want to back-annotate them.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    After doing above, where do I find these details in the GUI? Is it in Assignment Editor?

    How do I clear the location constraints and start anew?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    The fitter report exists after you've compiled, even if the pins weren't locked down. In the Quartus GUI, look at the compilation report and it's part of that. You could also look at the .fit.rpt.

    For back-annotating, I'm just saying now that they're assigned to those locations they'll show up in those banks in the Pin Planner if they weren't showing up before.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    The fitter report exists after you've compiled, even if the pins weren't locked down. In the Quartus GUI, look at the compilation report and it's part of that. You could also look at the .fit.rpt.

    For back-annotating, I'm just saying now that they're assigned to those locations they'll show up in those banks in the Pin Planner if they weren't showing up before.

    --- Quote End ---

    Perhaps u could help.

    compilation report> i/o assignment warning.

    "Missing drive strength and slew rate".... Implemented a simple AND gate on my device (STRATIX III), seems to me RED LED7 (my output pin assigned manually by me) comes ON alongside RED LED4 (compiler randomly assigned unused pin) and goes OFF alongside too. What can be done?