Feeling stupid - Reducing clock speed

Hello Pete,

From the code snippet I see that there is a mistake in the g_CLKS_PER_BIT calculation, which is supposed to represent the number of input clock cycles required to generate one bit of the output signal.

The value of g_CLKS_PER_BIT is calculated as 66_000_000/115200 = 572, which is incorrect. The correct value of g_CLKS_PER_BIT should be calculated as 66_000_000/115_200/2 = 284.72, which represents the number of input clock cycles required to generate half of one bit of the output signal. This is because the process generates a square wave with a 50% duty cycle, which means that it takes two clock cycles to generate one full bit period.

Since the r_Clk_Count signal is incremented by 1 on each clock cycle and the output signal is generated on every second cycle, the actual output frequency will be half of the expected frequency, which is 57.6 kHz instead of 115.2 MHz.

To fix this issue, you should update the g_CLKS_PER_BIT constant to the correct value of 284.72, which represents the number of input clock cycles required to generate half of one bit of the output signal.

The updated code should look like:

library ieee;

use ieee.std_logic_1164.all;

entity BaudClockGenerator is

port

(

Clk : in std_logic;

OutClk : out std_logic

);

end entity;

architecture rtl of BaudClockGenerator is

CONSTANT g_CLKS_PER_BIT:integer:= 66_000_000/115_200/2;

signal r_Clk_Count : integer range 0 to g_CLKS_PER_BIT-1 := 0;

signal tmp : std_logic := '0';

begin

BitPeriodProcess:process(Clk)

begin

if rising_edge(clk) then

r_Clk_Count <= r_Clk_Count +1;

if r_Clk_Count > g_CLKS_PER_BIT -1 then

r_Clk_Count <= 0;

tmp <= NOT tmp;

end if;

end if;

outClk <= tmp;

end process;

end rtl;

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