Ethernet ping issue with Arria 10 Development Kit

Hi Biswajit, I found out about one A10 TSE reference design but it’s just tested the MAC functionality only. User needs to add own design for TCP/IP testing. • https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/arria-10-single-port-triple-speed-ethernet-and-on-board-phy-chip-design/ 1. For internal loopback within FPGA TSE IP • TSE IP user guide is available in below link • https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf • You can refer to chapter 4.1.9 for the “MAC local loopback” and chapter 4.2.8 for “PHY PCS/PMA loopback” 2. For on board external PHY chip loopback • You can refer to PHY chip datasheet for the register setting or consult the PHY chip vendor for support 3. For on board external host loopback • You can check your board to see whether it’s able to perform cable loopback somewhere on board Thanks. Regards, Deshi