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Honored Contributor
Honored ContributorErrors linking Modelsim BFM models
Hi, I am trying to run a Verilog simulation of a test bench generated by Qsys 14.0 of a system that includes an ARM SoC HPS block. The originally generated test bench from ip-make-simscr...
Altera_ForumHonored Contributor
Honored ContributorThe “Bad library format” errors usually occur if the simulation libraries were compiled with a different simulator version other than version you are running now.
Try remove the entire compiled database and recompile with your Questa 10.3c. .