Forum Discussion
ShengN_altera
Super Contributor
2 years agoHi,
In Quartus Standard, go to Assignments -> Settings -> Simulation -> More EDA Netlist Writer Settings -> Generate third-party EDA tool command script for RTL functional simulation (on) -> Include test bench in Compile test bench: box -> run full compilation -> should see .do file auto generated in .../simulation/questa directory. Try to run the .do file and see the error still persist? (Note: remember to include the .sip file for compilation if there's any).
Also can try nativelink simulation should be no error given.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.