what "include" statement means that replace the statement from the file.
what you did is compiling just numbers in VerilogHDL.
that doesn't make sense.
in term of $fopen case.
actually verilog-HDL does support $fopen.
but QuartusII does not support some case of Verilog rules.
how about that prepare file like that
//-----------------------------------------------
`define MYNUMBER 32'h00FF00FF00FFFFF
//-----------------------------------------------
and use the definition in your code.
//-----------------------------------------------
fileID = `MYNUMBER;
//-----------------------------------------------
does it help for you?