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yy1's avatar
yy1
Icon for New Contributor rankNew Contributor
5 years ago

Error 18694 The reference clock on pll "name"

Quartus Version: Quartus Pro 20.4 Device family: Cyclone 10 Gx Issue : error 18694 The reference clock on pll "name", which feeds an altera lvds serdes ip instance, is not driven by a dedicated r...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,


I tried to recreate the scenario but am not getting the error. First created a project in v18.1, targeted to Arria 10, generated an LVDS SERDES IP instance with internal reference clock and ran the fitter. It ran without any errors.


Next I created another project in v20.4, targeted to Cyclone 10 GX and imported the above created IP .qsys file. The tool asked for the IP upgrade, so followed the steps and did an Auto Upgrade of the IP. Next I regenerated the IP files and ran the fitter. This also passed the Fitter stage without any errors.


In both the project. tool was allowed to do the pin placement automatically.


Is it possible to isolate and provide us the Cyclone 10 GX design portion which is creating the issue?


Regards.