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Altera_Forum
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13 years ago

Error (12061): Can't synthesize current design -- Top partition does not contain any

Hello people, I'm trying to compile the following code (below this paragraph) on Quartus II, I wrote the system verilog code on the altera modelsim program, there everything compiles and simula...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Wow! Is it just that? Add the output and it works? I was startting to rework the whole code to make it more low level... I will try the changes you made and will get the results... One question which device family you used? (I don't have a clue which one I should use, I just chose a random one)