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Altera_Forum
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13 years ago

Error (12061): Can't synthesize current design -- Top partition does not contain any

Hello people, I'm trying to compile the following code (below this paragraph) on Quartus II, I wrote the system verilog code on the altera modelsim program, there everything compiles and simula...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

I was finally able to get to a computer with the latest tools and it turns out Daixiwen is correct regarding the need for output ports. As a test case I added a 32 bit output called "out" and assigned the value of "K" to that output in the initial process and the code compiles fine.

The changes I made were: 


module DefRFID(testout);
output  testout;
....
....
initial begin
....
K = pertubationfunction....
out <= K;