Honored Contributor
Honored ContributorI don't know a lot about Verilog, but it looks like your module doesn't have any output ports. Quartus synthesizer is quite smart, and if it sees the code you wrote won't generate any signal out of the FPGA, it will "optimize" it by taking averything away, as the functionnal result will be the same. So you should first make sure any results from your algorithm get one way or another to one or more FPGA pins.
Second (but again I don't know a lot about Verliog) your code looks like a transcription of a software algorithm, and indeed it may result in a very complicated synthesized designed with lots of hardware in parallel. You will probably have to redesign a bit, add a clock signal and a sequencer to share resources over several clock cycles.
