Error 10479 : Indexed name type is used but not declared

Hi Guys,

Trying to run the code below gives me Error 10479 : Indexed name type is used but not declared at line 13 (The Function Return line). I'm a beginner in VHDL, but as I understand you don't need to separately declare a return variable or am I wrong? If so, how and where would I do that?

library ieee;

use ieee.STD_LOGIC_1164.ALL;

use ieee.STD_LOGIC_ARITH.ALL;

use ieee.STD_LOGIC_UNSIGNED.ALL;

entity bcdadder is

port ( SW : IN STD_LOGIC_VECTOR (9 downto 2);

HEX0, HEX1, HEX2, HEX3 : OUT STD_LOGIC_VECTOR (0 to 6);

KEY3 : IN STD_LOGIC);

-- FUNCTION to convert binary to bcd

function binarytobcd (binary_n : INTEGER RANGE 0 TO 15)

return STD_LOGIC_VECTOR (7 downto 0) IS < ERROR Line

VARIABLE out_v : STD_LOGIC_VECTOR (7 downto 0);

VARIABLE out_tem : INTEGER RANGE 0 TO 15;

begin

if (binary_n >= 10 and binary_n < 20) then

out_v (7 downto 4) := "0001";

elsif (binary_n >= 20 and binary_n < 30) then

out_v (7 downto 4) := "0010";

elsif (binary_n >= 30) then

out_v (7 downto 4) := "0011";

else

out_v (7 downto 4) := "0000";

end if;

if (binary_n >= 10 and binary_n < 20) then

out_tem := binary_n - 10;

elsif (binary_n >= 20 and binary_n < 30) then

out_tem := binary_n - 20;

elsif (binary_n >= 30) then

out_tem := binary_n - 30;

else

out_tem := binary_n;

end if;

out_v (3 downto 0) := conv_std_logic_vector(out_tem, 4);

return out_v;

end function binarytobcd;

end bcdadder;

architecture logic of bcdadder is

signal out_i: INTEGER RANGE 0 TO 30;

signal out_bcd, out_bcd2, out_bcd3, out_bcd4 : STD_LOGIC_VECTOR (3 downto 0);

signal a, b : INTEGER RANGE 0 TO 15;

signal outter, outera, outerb : STD_LOGIC_VECTOR (7 DOWNTO 0);

--COMPONENT INSTANTIATIONS

COMPONENT BCD2LED

PORT ( D:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

O:OUT STD_LOGIC_VECTOR(6 DOWNTO 0));

END COMPONENT;

begin

BCD1 : BCD2LED PORT MAP (out_bcd, HEX1);

BCD2 : BCD2LED PORT MAP (out_bcd2, HEX0);

BCD3 : BCD2LED PORT MAP (out_bcd3, HEX2);

BCD4 : BCD2LED PORT MAP (out_bcd4, HEX3);

a <= conv_integer(unsigned(SW(9 downto 6)));

b <= conv_integer(unsigned(SW(5 downto 2)));

out_i <= a + b;

switch_on : PROCESS (KEY3)

begin

outter <= binarytobcd (out_i);

outtera <= binarytobcd (a);

outterb <= binarytobcd (b);

if KEY3 = '0' then

out_bcd2 <= outter (3 downto 0);

out_bcd <= outter (7 downto 4);

out_bcd3 <= "XXXX";

out_bcd4 <= "XXXX";

else

out_bcd <= outterb (7 downto 4);

out_bcd2 <= outterb (3 downto 0);

out_bcd3 <= outtera (3 downto 0);

out_bcd4 <= outtera (7 downto 4);

end if;

end process switch_on;

end logic;