Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Error << TOP-LEVEL>>

Hi, I'm a new user to Quartus ii and i have a trouble when i m tring to do a syntesis and analysis for my circuit ; I have a message like error: Top-Level design entity "name of project" is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Do you have a verilog module or a VHDL entity named "name of project" ?

Is that file included in the project ?