Efficient State Machine Design

Here's my version of it.

//
// State Register and Outputs Register
//
always @(posedge clock) begin  // Sequential logic.
	state <= next_state;      // State Register
	outputs <= next_outputs;  // Outputs Register
end

Also needs a couple of more always blocks for the Next State Logic and Next Outputs Logic using combinational logic, e.g.:

//
// Next State Logic
//
always @* begin  // Combinational logic.
	if (reset) begin
		next_state <= STATE_RESET;
	end
	else begin
		case (state)
		.
		.
		.
		endcase
	end
end

//
// Next Outputs Logic
//
always @* begin  // Combinational logic.
 
	// Using a look-up table.
	if (reset) begin
		// Look ahead to the reset state for the next outputs.
		next_outputs <= outputs_table[STATE_RESET];
	end
	else begin
		// Look ahead to the next state for the next outputs.
		next_outputs <= outputs_table[next_state];
	end
 
	// Or alternatively without a look-up table.
	//case (next_state)
	//.
	//.
	//.
	//endcase
end