Efficient State Machine Design

The state machine code on page 11 of the document you posted is a good example of a one-hot encoded state machine.

To address another point made - yes, Quartus can be made to encode state machines as it sees fit or in a particular manner. However, it'll only do this if it can recognise specific bits of code you intend to be a state machine (Sree your request for a template is very sensible in this respect). Alternatively, you could use Quartus' built in state machine wizard to make it clear - not a route I'd consider.

Any FPGA design (that used Flip-flops) could be considered a state machine. I certainly don't want Quartus to determine what the best method of encoding my design. I (probably) want my N-bit counter remaining just that and not be turned into 2^N D-types. The same functionality could be realised. A counter is, after all, a state machine.

The point I'm making is that it is far better to understand what you want from your design, how you want it to be implemented and write the code appropriately. (Sree, I appreciate that seems to be what you're trying to do here.)

Cheers,

Alex