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Altera_Forum's avatar
Altera_Forum
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14 years ago

Early Power estimator Problem (Please help)

Hello,

Steps taken,

I generated my VCD file modelsim

I even converted it to wlf to make sure it was right

Output from estimator:

I/O Thermal power dissipation 2605mW

Core Dynamic power 446mW

Static Power 112.38mW


module topmodule1(CLK,RST,en,Xin,en_ram1,ram1_we_addr,en_ram2,ram2_we_addr,
                  out_ram2,in_ram2,rd_ram2,Yout);

input CLK;

input RST;

input en;

input [31:0] in_ram2;

input [31:0] Xin;

output reg [5:0] ram1_we_addr,ram2_we_addr;

output reg en_ram1, en_ram2,rd_ram2;

output reg [31:0] out_ram2;

output reg [31:0] Yout;

The addresses go to an external memory, and the "out_ram" are the datas from the external memory.

Attached are the pictures from the power analyzer

The power dissipated by the multpliers are 0. I am so confused because they synthesized (when I look at the number of multpliers).

Please help

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Could it be that my VCD file is wrong?

    I used the toggle rate 12.5% with no VCD file (toggle_rate.jpg)

    then i set the toggle rate to 50% with no VCD filter (toggle_rate_50.jpg) and the values make better sense