Different results with Quartus II 9.1 sp2 and Quartus II 7.2

I compiled an old verilog code (which was previously compiled with "Quartus II 7.2") with "Quartus II 9.1 sp2" and found different results.

Specifically, some numbers treated as signed in 7.2 are being treated as unsigned in 9.1 sp2 though they are declared as signed. I have no idea what is happening!!

can somebody help me??