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HugoStein's avatar
HugoStein
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3 years ago
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Dicrepancy between compiled projects in Quartus II Prime

Hello, Im trying to build a project that contains a lot of sub modules in quartus and, trying to debug the system because of a supposedly malfunctioning module, I found out that, if I compile the ...
  • _AK6DN_'s avatar
    _AK6DN_
    3 years ago

    Well if that indeed is your top level schematic, you have wired channels A...H and the trigger all to the same 16b bus.

    So it is not surprising at all that logic is eliminated.

_AK6DN_'s avatar
_AK6DN_
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

When compiled as a top module, all inputs and outputs are assumed to be used by Quartus, and the logic is generated.

Once instantiated as a sub module, Quartus can detect unused logic paths, and remove them.

Probably what you are seeing happen.

HugoStein's avatar
HugoStein
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3 years ago

Oh, I see.

At first, I thought there was some misconnection in the system, but my knowledge of quartus with block diagram is limited, so I didn't find a proper way of checking. Given that I'm using symbols in the block diagram with Verilog code as shown in the images below, do you have any suggestions?

Thank you so much for the reply,

Best regards,

Hugo Stein