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xiaobai1's avatar
xiaobai1
Icon for New Contributor rankNew Contributor
4 years ago

Development board outputs clock signal

I have encountered some problems in the process of learning. I sincerely hope you can spare time to guide me. Objective: To obtain 50MHz clock signal by using CycloneV (5CGTFD9E5F35) to output o...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

The input clock of 50MHz should be taken from V28 pin of FPGA and connect to sys_clk of your pll instance. IO standard should be 1.5V CMOS.


Regards