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New Contributor

3 years ago

Development board outputs clock signal

I have encountered some problems in the process of learning. I sincerely hope you can spare time to guide me. Objective: To obtain 50MHz clock signal by using CycloneV (5CGTFD9E5F35) to output o...

sstrell

Super Contributor

3 years ago

Assuming this is the board you are using (https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/cyclone/v-gt.html), J4 connects to U3, not the FPGA.

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Development board outputs clock signal

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