Forum Discussion
alex_ander
New Contributor
New Contributordetermining set input and set ouput delay values
Hello
I am working with understanding the timing analyzer and I have a question regarding the delay values themselves that would be used for the set_input_delay and set_output_delay. I understand s...
sstrell
Super Contributor
Super ContributorThe numbers come from the spec sheet of whatever is driving into the device (tco max and min) or whatever the FPGA is driving out to (tsu and th). I usually call them the upstream and downstream devices.
