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alex_ander's avatar
alex_ander
Icon for New Contributor rankNew Contributor
4 years ago

determining set input and set ouput delay values

Hello I am working with understanding the timing analyzer and I have a question regarding the delay values themselves that would be used for the set_input_delay and set_output_delay. I understand s...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
4 years ago

The numbers come from the spec sheet of whatever is driving into the device (tco max and min) or whatever the FPGA is driving out to (tsu and th). I usually call them the upstream and downstream devices.