Debug one-hot SM w/ 2 states active: look at actual SM bits?

The representation of the initial state in SignalTap may depend on the netlist type of the signal, in most cases, it's shown with correct polarity, inactive state = L. Without using the state machine safe coding option, you have a certain chance that the state machine gets caught in an illegal state, once it was entered e. g. due to timing issues.

Generally, a rich source of timing problems and all kinds of unexpected logical behaviour is the processing of asynchronous external signals. If they are used in more than one logical term without an additional synchronisation FF, the state of the signal may be seen different in two places for the same clock edge. A signal, that advances a SM state, may be seen in the expression, that sets the new state and not seen where the old state should be deasserted. As a result, both states may get active. The probability of such events increases with slow transitioning signals, but also exists with good quality digital signals.