Debug one-hot SM w/ 2 states active: look at actual SM bits?

Note that SMs are generally not encoded as one-hot but as "Altera one-hot". What this means is that the bit representing your reset bit will power-up to 0 and have not gates put before and after(also called not-gate pushback). So taking an encoding that you think of as:

0001

0010

0100

1000

If you look at the actual registers directly, it will be:

0000

0011

0101

1001

As I mentioned, a not-gate is added before and after this reset bit, which is absorbed for free into upstream and downstream logic. So all logic based on this bit will see it as the inverse, i.e. it will be active high. And all logic that would send it to be active high will get inverted and send it low. The net sum is your state-machine works exactly as it should in the system, and the only "strange" thing is that if you look directly at the register with SignalTap, it looks like it's inverted.

Another place to look is in the Compilation Report -> Analysis & Synthesis -> State-Machine Optimizations, and it should show the encoding there(assuming synthesis recognized it as a state-machine). This is also in the .map.rpt.

I'm not sure exactly how SignalTap interprets states though. It might try to do things in the intended manner(show a 1 when in that state), or the actual representation(where IDLE is 0 only in the IDLE state). It sounds like you're seeing the first case.

As for your issue, is the behavior consistent or occasional. Haveing a floating input control a SM is not just an issue that it's inconsistent behavior, but the SM registers could go metastable if this input transitions near a clock edge, and SMs(as most control logic) do not handle metastability and can cause all sorts of strange issues.