Forum Discussion
Altera_Forum
Honored Contributor
15 years agoSo far I have the following code...
architecture structural of SRAM_16bit_512K is begin process(iCLK) begin SRAM_OE_N <= iREAD; SRAM_WE_N <= iWRITE; if ( iCLK'event and iCLK = '1' ) then if ( iWRITE = '0' and iREAD = '1' ) then SRAM_CE_N <= '0'; SRAM_ADDR <= iADDR; SRAM_DQ <= iDATA; elsif ( iWRITE = '1' and iREAD = '0' ) then SRAM_CE_N <= '0'; SRAM_ADDR <= iADDR; oDATA <= SRAM_DQ; end if; end if; end process; end structural; is this correct? It seems to be reading and writing to and from the SRAM correctly but I'm not sure...