DE1 Reading / Writing to SRAM

Hello,

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...we are told that oCLK must determine the read / write cycle time.

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There is no CLK for the SRAM in the datasheet. So, your SRAM is asynchronous. This actually makes the design easier than say SDRAM controller.

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I really just need someone to point me in the right direction and get me started with this. I've never done anything with SRAM on the DE1 board (Or SRAM at all for that matter) and could really just use some guidance on designing this controller...

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Start by going through the datasheet for the SRAM on the DE1 system CD. Specifically pay attention to the timing diagrams for read and write cycle (p. 6 and p. 8 in the datasheet on v0.8 of the CD).

Next go through the reference designs. The file SRAM_16Bit_512K.v from the DE1_SD_Card_Audio project on the DE1 system CD should be useful. That file should hopefully show you how simple the SRAM interface is (again, because it is asynchronous).

Here is a link to a previous post which has a DE1 SRAM interface in VHDL from my colleague:

http://www.alteraforum.com/forum/showthread.php?p=104287#post104287

The VHDL design above is a little complex because it loads image data stored onto SRAM via the control panel.

Hope this helps, good luck.

Bart