DCFIFO recovery and removal problems

The global clock trees are all long. (Note that >3ns is that long for something that fans out to every register in the device.) The PLL phase-shifts the clock it sends out back in time to compensate for this, so it still has the long delay, it just starts earlier.

If it started at dac_fifo_clr_flopped, then it's not really doing a correct analysis. Let's say you had two designs, one where the clock delay to that flip-flop is 3ns, and one where it's 23ns. Wouldn't those two designs behave differently? The latter would fail timing analysis because the signal sent out by dac_fifo_clr_flopped wouldn't get to its destination in one clock cycle. It needs to trace the clocks back to their source(which is usually common) so it can calculate how much they deviate(skew) from each other going to the source and destination register. This is identical to clock skew when feeding the source and destination registers of setup analysis(synchronous, register to register analysis)