DCFIFO recovery and removal problems

Thanks for the reply Rysc.

Yes you are right, I am driving the source register with a clcok that doesn´t come from the PLL, and I am driving the destination with a clock that is derived from a PLL.

I don´t understand very well the reason for the long delay between the clock and the source register. I have attached a jpeg showing the full path of the clock. I don´t understand well why timequest is concerned with this long delay? Why doesn´t timequest start its timing analysis when the dac_fifo_clr_flopped signal is assinged? I´m sure there is a perfectly good explanation for this but I am having a little trouble getting my head around it.

Anyway out of reset the write enable lines are disabled, so I am going to cut the paths between both clocks. This should solve the problem, but for interest sake, I would like to get a better understanding of the reason for the long delay above.

Many thanks for the help