DCFIFO recovery and removal problems

Why does the clock to your source register go through a long delay and the clock to your destination register go through such a short delay? Run report_timing with the -detail full_path, but my guess is that you're driving the source register with a clock that doesn't go through a PLL, but the destination is driven by the PLL. I would move the source register to also be driven by the PLL output. The clock delay is valid.

Finally, if you have the write signal disabled out of power-up, then the DCFIFO doesn't care about the reset signal timing, as nothing is happening out of power-up(I'm assuming you didn't disable the checks that disallow overflow/underflow). So if that's the case, you could make this a false path.