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Altera_Forum
Honored Contributor
Honored ContributorCustomized signal
Hello, for my project, i need to generate an input that is customizable. Means that i want to customize the high state and low state. For example, I set 1 sec for high state and 0.5 sec for low state. How can i set this kind of signal from vhdl ? Any ideas ? Thank you in advance.
10 Replies
Altera_Forumuse a counter to count out 1s and 0.5s. Then toggle.
- Altera_Forum
what do you mean by toggling both counter ?
- Altera_Forum
Use a counter to count out the time. Then set your signal as you want at the appropriate time.
- Altera_Forum
D you have any example ?
- Altera_Forum
signal cnt : unsigned(31 downto 0); process(clk) begin if rising_edge(clk) then cnt <= cnt + 1; if cnt = ONE_S then op <= '1'; elsif cnt = ONE_S_PLUS_0_5s then op <= '0'; end if; end if; end process; - Altera_Forum
Thank you !
- Altera_Forum
Do I need a loop for this signal to repeat infinitely ?
- Altera_Forum--- Quote Start ---
--- Quote End --- Tricky, I am a bit disappointed...no clocking this timesignal cnt : unsigned(31 downto 0); process(clk) begin cnt <= cnt + 1; if cnt = ONE_S then op <= '1'; elsif cnt = ONE_S_PLUS_0_5s then op <= '0'; end if; end process; - Altera_Forum--- Quote Start --- Do I need a loop for this signal to repeat infinitely ? --- Quote End --- No, it is a continuous logic by itself but you need to add clock edge and your counter will keep going for ever.
- Altera_Forum--- Quote Start --- Tricky, I am a bit disappointed...no clocking this time --- Quote End --- Doh - fixed it.
