Honored ContributorHello, for my project, i need to generate an input that is customizable. Means that i want to customize the high state and low state. For example, I set 1 sec for high state and 0.5 sec for low state. How can i set this kind of signal from vhdl ? Any ideas ? Thank you in advance.
Honored Contributoruse a counter to count out 1s and 0.5s. Then toggle.
Honored Contributorwhat do you mean by toggling both counter ?
Honored ContributorUse a counter to count out the time. Then set your signal as you want at the appropriate time.
Honored ContributorD you have any example ?
Honored Contributor
signal cnt : unsigned(31 downto 0);
process(clk)
begin
if rising_edge(clk) then
cnt <= cnt + 1;
if cnt = ONE_S then
op <= '1';
elsif cnt = ONE_S_PLUS_0_5s then
op <= '0';
end if;
end if;
end process;
Thank you !
Honored ContributorDo I need a loop for this signal to repeat infinitely ?
Honored Contributor
signal cnt : unsigned(31 downto 0);
process(clk)
begin
cnt <= cnt + 1;
if cnt = ONE_S then
op <= '1';
elsif cnt = ONE_S_PLUS_0_5s then
op <= '0';
end if;
end process;
