Forum Discussion
Altera_Forum
Honored Contributor
13 years agoAnytime a register's output drives the clock port of other registers, i.e. a ripple clock, then a create_generated_clock must be applied to the register. I'm not completely sure why, but assume that since a register will always change the frequency, just passing the base clock through is incorrect. In your case, probably something like:
create_generated_clock -name "ripple_clk_2mhz" -source [get_ports sys_clk] -divide_by 16 [get_keepers {global_signals:inst|pll_ctr:inst3|lpm_counter:LPM_COUNTER_component|cntr_c8i:auto_generated|counter_reg_bit[0]} Obviously the name, source and divide_by need to be changed. Note that the -source is always a physical node in the design, not a clock that was created in your .sdc. (TimeQuest finds the clock on that physical node and uses it through). If you have ripple clocks feeding ripple clocks, then you need a generated clock at each stage. Hope that helps.