Honored Contributor
Honored ContributorOk, I have to blame myself and you may as well...
I did some further checks, used the initial programming file generated with QII 11.1 SP2 and recompiled with QII 12.0 to check, if there is a difference, well there wasn't and I even did not got my problem again... Ok, to cut a long story short: The value to be limited (RAG) is calculated as 32Bit vector by RAG = kp*(FG-RG-Offset). with Kp being a gain and FG as the demand (both via CAN), RG is the actual value (by external sensors) and the Offset is measured on power up and should be nearby zero (the system is normally well trimmed). As I had to change the ADC between my development units and this prototype the Power-UP timing changed and the Offset was measured during system voltages (in the analog circuit) stabilizes (not being stable). Thus the offset was far from zero (as I believed)... To complete the list of faliures of mine, I visualized the limited RAG using a panel in CANoe (CAN-Tool), having this box configured to show IEEE values rather binary coded one... As I started with: I'm to blame... Well - normally I use the JTAG I/F during development (thus voltages are stable when FPGA starts) but (when things go wrong...) that case I had only access to the active serial I/F and thus system started from the scratch (with the voltages rising and so on). This resulted in a permanent offset which caused the switchover from -1LSB to 0 at FG = 0 and RG = 0 but at FG = -Offset... which was half the maximum (well, when things go wrong)... But: I learned that I should replace the used libraries :-) Sorry for causing confusion, Carlhermann
