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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Connect split bus in verilog to output

Hello, I believe this is a really easy question, but I have searched how to do it for a long time and I still can't figure it out. I am just now switching from VHDL to verilog. I want to c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

you could always used name association, rather than inplied association (which is confusing as you have found) 


my_module inst_my_module
(
  .rx_in( rx_in ),
  .rx_outclock( rx_outclock ),
  .rx_out( { data_out, sync_decode_signal } )
  ... etc
);

Also, why not be more explicit with your ports. Your code uses Verilog95 style. This was updated in 2001 to be more like VHDL (and much easier to follow): 


module Tau2_LVDS(
input rx_inclock;
input  rx_in;
output rx_outclock;
output  data_out;
output sync_frame_start;
output sync_line_valid;
output sync_data_invalid;
);