Confused with set_input/output_delay command

Thanks for the detailed information. That is extremely useful but I still have a couple of questions. I believe this is for non source synchronous transfer. What if I have a transfer like in the attached picture

1) Aren't the delay fixed for both registers (last reg in FPGA A and first reg in FPGA B which is in the hardblock DDIO cell) and the clock path to both registers? If yes, how do Quartus actually try to optimize the timing (try to get as fast as it can)?

2) If this is a source-synchronous Edge-aligned transfer, can the same method/order of constraints be applied? If we constrain FPGA B first, how do we then constrain FPGA A since the setup relationship will be 0ns and Hold Relationship = -1/2 clock period?