Confused with set_input/output_delay command

That one is a pain because both sides are flexible. Here's the method I use. In the example, FPGA_A drives to FPGA_B and the clock period will be 10ns.

1) I start by overconstraining the driving FPGA first. You could do either one, but that one is usually easier to understand. So something like:

create_clock -period 10.0 -name FPGA_A_clk [get_ports A_clk]

create_clock -period 10.0 -name ext_B_clk

set_output_delay -clock ext_B_clk -max 10.0 [get_ports A_outputs*]

So I have a 10ns setup relationship and say the external device has a 10ns delay, so I am asking the FPGA to have a Tco of 0ns. It will fail timing, but it will try to get as fast as it can.

2) I compile and see that it fails by -6ns, i.e. FPGA_A has a Tco of 6ns. So now I loosen the requirement to get that to pass:

set_output_delay -clock ext_B_clk -max 4.0 [get_ports A_outputs*]

I may also add a simple hold time at this point. Hold is not a concern, since the hold requirement is 0ns and as long as the delay across the interface is greater than 0(or greater than the clock skew if there is large skew), we'll meet timing. But something like:

set_output_delay -clock ext_B_clk -min 0.0 [get_ports A_outputs*]

(You could also look at the worst case hold skew and constrain based on that. So if it makes timing by 2.5ns, then do a set_output_delay -min -2.5ns, which means the FPGA_A must have an output delay greater than 2.5.ns to meet timing. But do not do hold until you've gotten the best setup, as you don't want the fitter to add delay to meet hold at the expense of setup)

I recompile and make sure it is still meeting timing.

3) At this point I have fixed one side. I then constrain FPGA_B to say it's external delay based on FPGA_A:

create_clock -period 10.0 -name FPGA_B_clk [get_ports B_clk]

create_clock -period 10.0 -name ext_A_clk

set_input_delay -clock ext_A_clk -max 6.0 [get_ports B_inputs*]

set_input_delay -clock ext_A_clk -min 2.5 [get_ports B_inputs*]

If FPGA_B meets timing, technically you're done. To add board delays, I would just add it to the one that has slack, i.e. FPGA_A barely meets its 6ns Tco requirement, but if FPGA_B has 500ps of slack, and the board delay is 300ps, then increase the max delay to 6.3ns on FPGA_B's max input delay.

Often you have lots of slack, and we've constrained A to be as tight as possible. Let's say the clock period is 20ns, and after following these steps FPGA_B has 8ns of slack, while FPGA has hardly any. You can loosen the requirements on A and tighten them on B the same amount, but it's not necessary.

The basic idea though is to get one FPGA to get "the best timing" that it can, then use that to constrain the other one. (There are other scenarios. If the interface is slow, just give them both roughly half the data period and be done with it, as you know it meets timing)