Confused with set_input/output_delay command

Yes and no. When we talk about the values for set_input/output_delay, then the clock edges do not matter. But for the entire setup analysis, they do matter. For example:

10ns clocks, and FPGA is transmitting to an external device who has a Tsu of 4ns. That 4ns is the data_delay-clock_delay inside the external part, but it is 4ns no matter what edges we are talking about.

Let's say the FPGA has a Tco of 8ns and board delay is 0.5ns. The default setup relationship is 10ns, i.e. we launch at edge 0ns and latch at edge 10ns. The data arrives at 8 + 0.5 + 4 = 12.5ns and it fails timing by -2.5ns.

Now we add a multicycle to make the latch edge at times 20ns. The data_delay-clock_delay inside the external part is still 4ns and it still has a Tsu of 4ns. But now we meet timing by 7.5ns slack.

Similarly for setup and hold, the edges are used in calculating if we meet timing, but the external delays are usually independent of what those edges are.