Honored ContributorHello every body,
i am not sure how to explain this. When i added signaltap support in my project and i run it everything works perfectly. Then i remove the signal tap support and my logic is not running properly. Did any of you had similar issues? How did you resolve them? What is the cause of this? Regards
Honored ContributorI assume you recompiled from scratch? That causes a whole new place-and-route, which changes the timing on everything in the design. Usually I've seen this when something is unconstrained or incorrectly constrained, and so it still passes timing analysis in both cases, but this "incorrect" portion fails in one and not the other.
You'll want to lock everything down and run SignalTap on that. Hopefully you still have the original design, make a copy of it. Open Assignments -> Design Partition Window and you should see the partition Top(and any others you may have created). Set it's Type to Post-Fit, which will preserver the placement and routing. SignalTap is always in another partition, and so it will be placed and routed around the design that is now locked down. The only major caveat is that you have to use post-fit nodes, because it can't resynthesize. I recommend only tapping registers. (Note that I'm assuming you've fully constrained the design with timing constraints. If you haven't then I would start there).Honored ContributorHi
thank you for reply. I usually construct my project from small independent modules. Have noticed that if i change something (maybe just an if condition) in one module the other (completely separate, no connection between them) starts to misbehave. Is this the same as with SignalTap? Also i have a quartus web edition so Assignments -> Design Partition Window i cant use :( regards
