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Altera_Forum's avatar
Altera_Forum
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12 years ago

Comparison with 0 or 1, to detect high impedence

Hi, I know that its not allowed to compare with 'X' or 'Z' in a synthesizable VHDL code. But is it allowed to write a code in which I compare a signal to '0' or '1' to detect an 'Z' and susp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I think Quartus doesn't like tristate signals inside FPGA.

Tristate is for pins.