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Altera_Forum
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12 years ago

Comparison with 0 or 1, to detect high impedence

Hi, I know that its not allowed to compare with 'X' or 'Z' in a synthesizable VHDL code. But is it allowed to write a code in which I compare a signal to '0' or '1' to detect an 'Z' and susp...
Altera_Forum's avatar
Altera_Forum
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12 years ago

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there is no casez in VHDL

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Furthermore, the value z in Verilog casez means a don't care value for synthesis, not a test for z state. See 1364.1 ieee standard for verilog register transfer level synthesis

z can't be used in compare expressions in synthesized Verilog, in so far it's the same thing as in VHDL (not surprizing).