Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Comparison with 0 or 1, to detect high impedence

Hi, I know that its not allowed to compare with 'X' or 'Z' in a synthesizable VHDL code. But is it allowed to write a code in which I compare a signal to '0' or '1' to detect an 'Z' and susp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

--- Quote Start ---

But is it allowed to write a code in which I compare a signal to '0' or '1' to detect an 'Z' and suspend the operation?

--- Quote End ---

Allowed, yes. Meaningful, no.

reg_0(0) = '0' or reg_0(0) = '1' simply compiles to TRUE

Consider how 'Z' state would be detected in hardware and you'll hopefully understand why the code can't work.