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Altera_Forum's avatar
Altera_Forum
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16 years ago

Clock domain crossing of a gray counter. Any constraints / directives / cells?

I have two unrelated clock domains 50MHz / 133MHz > reg clk50; > reg clk133; I am implementing a Fifo between two clock domains. and have gray counters crossing the clock domains....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks I'll do some reading.

Currently I just created a quartus project, added all verilog sources and started compiling with quartus_sh --flow compile

I even don't know what I'm using in the moment ( TAN or Timequest )