Clock domain crossing of a gray counter. Any constraints / directives / cells?

Hi Rysc,

Thanks for your answer:

The reason why I don't use the mega functions:

- I don't know quartus that well

- I'd like to learn

- I'd like to implement a Fifo, that can be used with Altera, Xililnx and perhaps even with Silicondesign flows and the minimum of `ifdefs / specific blocks

For my use case comparing the values would be good enough.

The write pointer is controlled by the same clock domain as the full flag, so having a delayed version of the read pointer would only pretend, that the Fifo were fuller than it really is.

The read pointer is controlled by the same clock domain as the empty flag, so having a delayed version of the write pointer would only pretend, there's less data to fetch there really is.

if I really had to perform write / read pointer calculus, then I could perform a gray to normal conversion and perform the comparisons or other arithmetics.

My main difficulties are:

- do I need double retiming for gray counters / are there any special cells / coding styles for resynchronizing flip flops between two clock domains

In case of doubt I would just double retime, the counter bits.

- where and how do I specify the constraints.

Currently I used quartus to create a project, selected the target device,

added all verilog sources.

I then perform the compilation via

quartus_sh --flow compile

How to and whre can I add constraints to ignore signals crossing clock domains (or is there something like a global switch to say:

"Please ignore ALL transitions between clock1 and clock2 ?