clock definition

For timing, I might recommend:

http://www.alterawiki.com/wiki/timequest_user_guide

(I'm biased because I wrote it).

If a design has no .sdc, TimeQuest goes in adds high-speed clock constraints. This is called "benchmark" mode for the user who creates a quick project with some test HDL to see how fast it runs and they don't bother with an .sdc. Without a constraint it used to not optimize for timing and Altera would look bad in these benchmarks.

As soon as the user starts creating clock constraints in an .sdc, TimeQuest assumes you know what you're doing and will no longer constrain stuff that doesn't have a constraint. You can always run the Report Unconstrained Paths and it will show you all the locations that drive clocks that don't have a constraint.

In essence, TimeQuest knows what drives the clock ports of registers. In benchmark mode it tries to constrain them with something that was impossible(may be possible in Stratix 10), and in normal mode where a user has constraints, Report Unconstrained Paths can help.