clock definition

Thank you a priori for your kind replies.

As I stated, I am quite new to all this.

I am quite familiar with CS as well electronics (digital and analog) I just am new to all this EDA.

I am teaching myself Verilog and VHDL currently.

I tried The Xilinix ISE and like quartus better.

But more to the point. I understand your point about clock constraints.

I think more to what I was asking is if you donot define a clock constraint and run full compile the software will still define a clock of default 1 Ghz (i understand this is for testing only) and attach it to a pin (the clock pin).

Does it look for a pin named clk or clock to know where to attach it or as stated by previous responder is able to tell by structure of behavioral code and registers load if doing gate level modeling?

thank you all again for helping me.

Oh by the way. I find the quartus handbook (which I have read as well was taken a few quartus online courses) quite convoluted.

Any better source to learn?

thank you.

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Create an .sdc file. Put in the following:

create_clock -period 10.0 -name clock [get_ports {clock}]

derive_pll_clocks

Change the clock to whatever the name of your top-level port that a clock comes in on. The -name can be whatever you want. Make the -period value correct. Add as many create_clock constraints as necessary.

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