Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

clock definition

I know this is probably going to be a stupid question. I have just started using quartus and doing HDL so please bare with me. I was just wondering how the software knows what the clock line is in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

From your code it infers a load of registers, and from that its quite easy to infer which signal is the clock.

The 1GHz default constraint is unrealistic, and just put there to see what the real FMax is. The best you can get in the newest devices is about 400+ MHz with serious design considerations.