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Honored Contributor
Honored ContributorChannel Deadlock Debugging
I've developed a design in which there are 4 NDRange kernels all running concurrently on the FPGA and communicating with each other via the Altera OpencL Channels extension. There are many channels i...
Altera_ForumHonored Contributor
Honored ContributorTry using non-blocking reads and/or writes to the channel to avoid deadlock. In one of my designs I use a non-blocking read inside a do-while loop which effectively polls the channel until something is received:
bool got_val;
do{
read_val = read_channel_nb_altera(accum, &got_val);
}while(!got_val);
