Altera_Forum
Honored Contributor
11 years agoCan't get Qsys to generate a testbench for a custom component using exported signals
I’m trying to use Qsys 13.1 to generate a testbench for a custom component that uses one Avalon Slave interface and one conduit to export 4 signals. I know the component works, I use it in an existing design, I'm just trying to come up to speed on Qsys generated test benches.
I add my component as the sole component in a new Qsys system and export all the interfaces (clk, reset, avalon_save, conduit). When I generate the testbench it throws an error “Error: TB_Gen: Design has 4 but instance has 0 exported interface” If this worked, I thought it would attach an Altera Conduit BFM to the conduit interface of my component in the generated test bench.With that assumption, I tried piecing together the test bench by hand but when I connect the Conduit BFM to my conduit_end interface, it complains that they need to be on the same clock and reset domain, but the Conduit BFM doesn’t have a clock or reset interface. This seems like a simple thing that most everybody using a testbench would want to do frequently.The only tutorials that I’ve found use a FIFO or some other Altera component as a DUT which doesn’t export any signals. Can anyone point me to an example that could enlighten me on this subject? Thanks for your time!