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SivaKona's avatar
SivaKona
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Cannot place ALERT# in DQS group Error for External Memory Interfaces Intel Stratix 10 FPGA IP

Hi, We are working on Quartus Version : Quartus Prime Version 21.1.0 Build 169 03/24/2021 SC Pro Edition Target Device: 1SG280HU2F50E2VG Added "External Memory Interfaces Intel Stratix 10 FPGA ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Siva Kona,


Changed "ALERT# pin placement" from "I/O lane with DQSGroup" to "Automatically select a location"

Are these valid changes?

  • Yes the change is valid.


Do you see any error message in the qsys?


What is the DQ pins per DQS group that you used?


Regards,

Adzim